1. Field of the Invention
This invention relates to an improved method for testing integrated circuits (ICs) during the IC fabrication process. More specifically, the present invention relates to an improved method for using quiescent or transient current signatures to test for defective ICs during the IC fabrication process.
2. Description of the Related Art
Integrated circuits consist of a number of interoperable circuits fabricated on a silicon substrate. The number of interoperable circuits that can be supported by a substrate continues to grow as the art of IC manufacturing advances. Currently, it is not uncommon for an IC to include several million transistors configured into tens of thousands of interoperable circuits. While increasing the number of circuits that can be fabricated on a single IC allows designers to design smaller and faster products, such increases present the IC manufacturer with challenges in manufacturing fault-free ICs. One such challenge for manufacturing fault-free ICs is the difficulty in testing these ICs for defects in an accurate and efficient manner.
To facilitate IC testing, many different IC testing methodologies have been developed. These testing methods have been developed for evaluating any of a number of types of ICs, such as complimentary metal-oxide semiconductor (CMOS) ICs. These testing methods analyze the failure rate of the tested ICs so that substandard ICs are not distributed in the marketplace. These testing methodologies can be either built into the IC itself, or can be performed through the use of separate testing mechanisms.
Testing is usually performed to ensure proper logical operation of the ICs and to detect manufacturing defects in the components comprising the ICs. To ensure proper logical operation of the IC, the IC is stimulated using known test patterns and is monitored to determine its output response. If the resulting output response of the IC is as anticipated, it is assumed that the IC is functioning properly. For VLSI circuits, tens to hundreds of megabytes of test patterns are needed to test most of the IC. Such testing is extremely time consuming.
Testing methods include built-in-self test (BIST) circuitry, accelerated life testing (“burn-in”), functional testing, stuck-at fault (SAF) testing, quiescent current (Iddq) testing, and transient current (Iddt) testing, among other testing methods.
BIST circuitry is incorporated into the IC itself, and can constitute a significant portion of the circuitry on an IC, i.e., approximately 17%-30%. This BIST circuitry internally stimulates the IC in which it is incorporated, and measures the corresponding output response resulting from the stimulus. The problem with BIST circuitry is that it requires more hardware space on the IC as the number of gates or nodes on the IC increases. Thus, as the complexity of the IC increases, the amount of space on the IC surface necessary for testing circuitry increases. This can be extremely inefficient when the size of the IC is a concern.
Burn-in can be used to accelerate identification of latent IC defects created during either the IC fabrication process or the semiconductor assembly process. One example of a latent IC defect caused during the IC fabrication process is a defect in an oxide film of the IC, such as a pinhole in the gate oxide, while an example of a latent IC defect caused during the semiconductor assembly process is a crack in the sealing resin. Identifying and removing latent defects allows for higher reliability circuits to be supplied to IC users.
In the IC fabrication process, burn-in is performed by applying an environmental stress, such as high temperature/voltage to an IC being tested. During and/or after the application of this stress, the IC is monitored to determine whether it performs properly. The application of this environmental stress to the IC allows for the reliability of the assembled device (IC) to be ascertained.
The amount of time for which the electrical or environmental stress is applied to the IC must be determined experimentally. The stress should function to destroy or degrade performance in those ICs that are inherently defective, while having little or no effect at all on those ICs which are fault-free. Depending on the length of time for which the burn-in stress is applied to the IC, and the sample number of ICs that are burned-in, the burn-in process can result in anywhere from 5%-40% of the cost of producing an IC. In order to become more competitive in the marketplace, more efficient methods of failure analysis testing should be developed.
Another IC testing method is logic response stuck-at-fault (SAF) testing. Logic response SAF testing involves the application of stimuli to the inputs of a particular IC, and the examination of the IC outputs to determine if a particular internal fault exists in the IC. If a Stuck-at-fault exists for a given circuit node, that node will not toggle, and will be “stuck-at” either a 1 or a 0, such that the actual output response of the IC will not match the expected response. There are, however, some inherent problems with using logic response SAF testing to identify faults in a given IC. For example, it is difficult and costly to generate a sufficient number of input signal test vectors to detect a desired level of fault coverage Fault coverage is the percentage of all possible faults in a given IC that can be tested by a given set of test vectors. Also, it is extremely time consuming to measure the response of every circuit found in the IC. Furthermore, in circuits with inherently low controllability, such as those with random logic control circuits or those circuits with asynchronous designs, a large number of internal faults in the IC may not be stimulated, and will not be detectable at the output regardless of the particular stimuli applied. The desired fault coverage therefore may not be obtained for ICs using the SAF test. Secondly, many physical defects in an IC, such as bridging, gate oxide shorts, and spot defects, might not be detected using the SAF test. These defects can cause indeterminate logic levels at the defect site, and therefore cannot be detected by any logic testing method.
One alternative to the SAF test involves the use of a technique known as scan design. The scan design technique requires test structures to be incorporated into the IC in order to facilitate testing. Scan testing adds controllability to defective nodes, but does not guarantee that the defective response can be observed at the device outputs. Thus, as is the case with functional and SAF tests, stuck-at faults and physical defects such as bridging, gate oxide defects and spot defects, might not be detected by scan testing.
Another problem with adding scan structures into the IC is that these structures consume IC space and power—much like BIST. Additionally, depending on the placement of these scan structures, timing problems may be introduced into the IC. As a result, scan structures may be difficult to incorporate into an existing IC design. Thus, an IC typically must be designed from the outset to incorporate acceptable scan structures.
Another method of failure analysis testing is quiescent current, or Iddq, testing. Over the last 15-20 years, research has shown that a very effective method for screening out defective ICs, including certain CMOS-designed devices, that are at a fully static (or quiescent) state is to determine whether or not these ICs have higher than nominal background current levels. Fully static means that no internal nodes of the IC are changing state or switching, i.e., toggling between 0 and 1. Furthermore, nominal background current means that the fully static IC only draws current in its quiescent state due principally to sub-threshold and reverse-bias junction leakage of transistors, and the IC is in a low current state. Since a logical circuit can be represented by an interconnection of logical gates, such as and gates and or gates, any higher than nominal current in the fully static or quiescent state can be attributed to leakage current in certain defective gates of the IC.
The quiescent current method can be used to detect defects such as gate oxide leakage, stuck-at (nodes incorrectly tied to logic 0 or 1) defects, bridging (neighbor nodes accidentally tied together) defects, leaky p/n junctions (high reverse-bias leakage current), some forms of open circuits (disconnects in metal or polysilicon), low threshold voltage in transistors, punch through (drain and source of a transistor are electrically shorted together, rendering the affected transistors always on), and delay fault (where delay paths or transitions change functional behavior). Quiescent current testing is particularly applicable to circuits having CMOS and BiCMOS designs, for example, and other technologies that generally have low background current.
Quiescent current testing is based upon the fact that for a fully static CMOS IC, i.e., when all circuit nodes have voltages settled to a nominal value, virtually no current is drawn from the power source by the IC. Current drawn in the nanoampere (nA) range is also potentially acceptable, since a fault-free IC at a fully static state may still tend to draw low current levels from the power source, and higher nominal background currents may be seen for deep-submicron lithographies. Even though there is some measurable quiescent current in a fault-free IC, it is still possible to characterize an IC device as defective by measuring its quiescent current. When the quiescent current measurements in defective ICs are higher than the normal quiescent current level that is expected for the IC, the IC will be considered defective.
A high quiescent current measurement for at least one IC circuit node indicates that at least one location in the IC has a defect that is causing a leakage problem. In order to detect all possible locations for the gate oxide defects resulting in the high quiescent current, it would be necessary to toggle every transistor of the IC while measuring its quiescent current values. Such toggling could only be applied to each input of the IC for a period of 10's to 100's of milliseconds. Therefore, obtaining 100% test coverage of a VLSI IC chip, for example, can take up to hundreds of hours to complete. This amount of time is prohibitive, especially when hundreds of thousands, or even millions, of ICs are produced at each IC production site daily.
Multiple methods for performing quiescent current testing in ICs are currently known in the art. Perhaps the most commonly used quiescent current testing method is the single limit Iddq method. In this method, a quiescent current limit is experimentally selected. This quiescent current limit selection is based upon measurement of quiescent current in ICs determined to be defective and ICs determined to be fault-free using other testing methodologies. After these measurements are made and evaluated, a statistical approximation of what quiescent current value measurement identifies a defective IC. This quiescent current value is then set as the current limit for that type of IC. Once the current limit is set, any evaluated IC that has a quiescent current value greater than the current limit is considered to be defective.
As the number of transistors on an IC gets larger, and the lithography of the IC decreases, the quiescent background current of the IC increases. This increased background current will effect the quiescent current measurement of the IC, generally increasing this nominal quiescent current value and reducing the difference between the quiescent current of a defective IC and a non-defective IC. Therefore, it is difficult to use the single limit method to determine if ICs with a large concentration of circuitry are defective. Furthermore, the single limit method is also problematic because it treats all individual gates or circuits in the IC as homogenous, and fails to take into account the fact that different stimuli may cover more potentially defective portions or nodes of the IC than others.
An alternative to the single limit method is the current difference method. In the current difference method, a measurement is taken of the absolute difference between a first quiescent current measurement of the IC in its entirety and subsequent quiescent current measurements. This measured difference is potentially more effective than the single limit method at identifying faults in an IC, because the current difference method nullifies the effect of IC background noise on the outcome of the test. The background noise is nullified because it is incorporated into both measurements, and is thus irrelevant. The important value when using the current difference method is the difference between the two measured quiescent currents, and not the quiescent current measurements themselves. If the measured current difference is greater than a predetermined current difference limit, then the IC being tested is considered to be defective. Thus, even this method, like the single limit method, requires a current limit to be experimentally set. This current limit cannot be determined without experimentation, and even then the current limit arrived at may improperly identify some defective ICs as being fault-free.
An alternative test method to the single limit and current difference methods is called the current signature method. In the current signature method, multiple current limits can be set for the IC. A set of voltage vectors (or Iddq vectors) is applied to the IC, and, for each vector applied, a quiescent current measurement is made for the IC. Voltage vectors (or “vectors”) refers to voltage values applied as stimuli to the inputs of an IC; these voltage values correspond to logical 0's and logical 1's for the IC technology being used. The vectors will propagate through the IC gates and nodes to the IC outputs. The application of these vectors to the inputs of the IC will cause the gates or nodes within the IC to be set to a 0 or 1 logic level. For each vector applied, a current limit for the measured quiescent current value is set.
The first step of this method therefore requires that a set of vectors be generated, targeting maximum Iddq fault coverage. These “Iddq vectors” are applied to the experimental ICs, and a small subset of vectors are measured that represents the majority of fault coverage possible for the experimental ICs . For each vector applied to the experimental ICs, the mean and standard deviation of the measured quiescent current response for that vector is determined from a statistically valid cross-section of ICs known to be substantially fault-free. The mean and standard deviation of the quiescent current responses from these Iddq vectors can then be sorted in increasing order, and can be plotted graphically to depict a standard current signature for the given IC to which the Iddq vectors were applied.
In production testing, these Iddq vectors will be applied to ICs that are also commonly referred to as “devices under test” or “DUTs.” The mean and standard deviations for the measured Iddq vectors are not required to be sorted. However, if these values are sorted, they must be sorted in some order—either increasing or decreasing in value. Subsequently, vectors are applied to the DUT and measurements are made of the corresponding quiescent current responses. Upon the application of these vectors to the DUT, any of the multiple measured quiescent current response of the DUT that exceeds the predetermined limits provided by a standard current signature derived from experimental ICs results in the DUT failing the current signature method.
Not every defective IC to which vectors are applied will produce at least one quiescent current measurement that will exceed the predetermined limits. To identify these ICs as defective, another measurement method, such as the total variance method may be used. The total variance method differs from the vector-by-vector method by examining the totality of variances of the quiescent current measurements caused by the application of vectors to the IC, rather than individual quiescent current measurements caused by the application of these vectors. This total variance accounts for all of the individual variances of the quiescent current signature with respect to the standard signature for all of the vectors. If the total variance of an IC exceeds the total variance limit set, the IC fails the total variance test.
Methods for measuring quiescent current values work well for determining gate oxide leakage and most other problems in ICs having lithographies greater than 0.25 microns. However, quiescent current measurement analysis on ICs with lithographies less than 0.25 microns is less effective. The reason for this is that as the size of the IC becomes smaller and the density of gates on the IC for the surface area of the IC becomes larger, the IC has a greater amount of background leakage while in its static state. This background leakage prevents a proper monitoring of changes in quiescent current values in these ICs, since the difference between the defect current and the background current may be too small to measure, or may be entirely masked.
One technique for overcoming the limitation of measuring quiescent current values in sub-0.25 micron ICs involves the use of dynamic current testing for detecting defective devices. Dynamic current testing allows monitoring of power consumption by the IC during transient periods, i.e., when the gates of the IC are switching. This dynamic current technique is commonly referred to as transient current, or Iddt, testing. Historically, it had been believed that although a defective IC device may exhibit abnormal behavior in its transient current state, this abnormal transient current would be masked by the overall transient current of the IC, thereby preventing the identification of defective gates. Recent studies have shown that this masking does not necessarily occur.
One problem with the traditional implementation of Iddq testing is this method's inability to discern defect-free devices with currents elevated due to otherwise acceptable process variations from defective devices. For example, relatively small changes in the channel length of an IC can cause substantial changes in sub-threshold leakage currents of that IC. It is preferable to find a test method that accepts ICs having high leakages caused by normal process variations and reject ICs having high leakages caused by defects.